library IEEE;
use IEEE.std_logic_1164.all;
entity ALU_contoler is
	port(
		clk     : in  std_logic;
		rst     : in  std_logic;
		BTN0    : in  std_logic;
		RegCtrl : out STD_LOGIC_VECTOR(1 downto 0);
		FN      : out STD_LOGIC_VECTOR(2 downto 0)
	);

end ALU_contoler;

architecture implement of ALU_contoler is
	type state_type is (Reset, Read_A, Read_B, Add, Sub, Max, Rst_to_A, A_to_B, B_to_Add, Add_to_Sub, Sub_to_Max, Max_to_Add);
	signal state, next_state : state_type;

begin
	-- purpose: sequence detector
	combinational : process(clk, rst, BTN0)
	begin
		case state is
			when Reset =>
				FN      <= "111";
				RegCtrl <= "11";
				if ((rst = '0') and (BTN0 = '1')) then
					next_state <= Rst_to_A;
				end if;
			when Rst_to_A =>
				RegCtrl <= "01";
				if (BTN0 = '0') then
					next_state <= Read_A;
				end if;
			when Read_A =>
				FN      <= "000";
				RegCtrl <= "01";
				if (rst = '1') then
					next_state <= Reset;
				else
					if (BTN0 = '1') then
						next_state <= A_to_B;
					end if;
				end if;
			when A_to_B =>
				RegCtrl <= "10";
				if (BTN0 = '0') then
					next_state <= Read_B;
				end if;
			when Read_B =>
				FN      <= "001";
				RegCtrl <= "10";
				if (rst = '1') then
					next_state <= Reset;
				else
					if (BTN0 = '1') then
						next_state <= B_to_Add;
					end if;
				end if;
			when B_to_Add =>
				if (BTN0 = '0') then
					next_state <= Add;
				end if;
			when Add =>
				FN <= "010";
				if (rst = '1') then
					next_state <= Reset;
				else
					if (BTN0 = '1') then
						next_state <= Add_to_Sub;
					end if;
				end if;
			when Add_to_Sub =>
				if (BTN0 = '0') then
					next_state <= Sub;
				end if;
			when Sub =>
				FN <= "011";
				if (rst = '1') then
					next_state <= Reset;
				else
					if (BTN0 = '1') then
						next_state <= Sub_to_Max;
					end if;
				end if;
			when Sub_to_Max =>
				if (BTN0 = '0') then
					next_state <= Max;
				end if;
			when Max =>
				FN <= "100";
				if (rst = '1') then
					next_state <= Reset;
				else
					if (BTN0 = '1') then
						next_state <= Max_to_Add;
					end if;
				end if;
			when Max_to_Add =>
				if (BTN0 = '0') then
					next_state <= Add;
				end if;
		end case;

	end process combinational;
	sync : process(clk, rst) is
	begin
		if (clk'event and clk = '1') then
			if (rst = '0') then
				state <= next_state;
			else
				state <= Reset;
			end if;
		end if;

	end process sync;
end implement;